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[VHDL-FPGA-Verilog] USB_Interface

Description: verilog USB USB的slave fifo的控制-verilog USB
Platform: | Size: 2048 | Author: xuxf | Hits:

[OS Develop] SC16C752B

Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.
Platform: | Size: 160768 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] Verilog_USB_OUT

Description: USB out，使用Verilog写的，包含完整工程、文档和USB芯片的固件-USB OUT, VERILOG, Including project、document，USB firmware
Platform: | Size: 1153024 | Author: 严刚 | Hits:

[VHDL-FPGA-Verilog] ad_da_ctr

Description: 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simulation results are basically correct.
Platform: | Size: 2299904 | Author: ych | Hits:

[VHDL-FPGA-Verilog] AsynFIFO

Description: Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
Platform: | Size: 32768 | Author: 郑宇龙 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
Platform: | Size: 110592 | Author: 洪依 | Hits:

[Software Engineering] syn_fifo

Description: 基于systemverilog的异步fifo-fifo of design ，system verilog
Platform: | Size: 1024 | Author: weiwenqiang | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo designed by haneesh (me) in verilog-fifo designed by haneesh (me) in verilog
Platform: | Size: 2048 | Author: haneesh | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 采用verilog HDL语言实现FIFO的功能，内涵测试程序，有较强的使用性能。-Using verilog HDL language to achieve FIFO functionality, meaning the test program, there is a strong performance.
Platform: | Size: 28672 | Author: benzema | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 此程序为verilog语言，实现的功能为FIFO功能，包括三个部分，分别实现不同的功能。-This program is verilog language, functions as a FIFO function, consists of three parts, respectively, to achieve different functions.
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: verilog 实现FIFO存储功能，八位数据宽度，16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
Platform: | Size: 60416 | Author: liaoju | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用verilog实现FIFO，包含所有工程文件。-Verilog implementation using FIFO, includes all project files.
Platform: | Size: 1950720 | Author: 于志宏 | Hits:

[VHDL-FPGA-Verilog] FIFO-Design

Description: FIFO(first in first out)-first in first out, using verilog
Platform: | Size: 180224 | Author: 方舟 | Hits:

[VHDL-FPGA-Verilog] Verilog-FIFO

Description: 可综合的Verilog FIFO存储器，可以实现先如先出的设计-Synthesizable Verilog FIFO memory can be as-first-out design
Platform: | Size: 2048 | Author: 白白 | Hits:

[VHDL-FPGA-Verilog] USB_FPGA

Description: 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码（FPGA端程序）-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)
Platform: | Size: 1024 | Author: lee | Hits:

[VHDL-FPGA-Verilog] fifo_4X16

Description: 完整的FIFO Verilog程序，经过仿真验证，直接可用-FIFO Verilog
Platform: | Size: 211968 | Author: 杨剑 | Hits:

[VHDL-FPGA-Verilog] Asynchronous-FIFO-Design

Description: 异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
Platform: | Size: 3072 | Author: 林峰 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO的设计，用Verilog HDL语言编写-The design of FIFO,using Verilog HDL program language
Platform: | Size: 440320 | Author: Benny | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: Verilog代码，实现FIFO先入先出存储-FIFO CODE,VERILOG
Platform: | Size: 14336 | Author: 王毅 | Hits:

[VHDL-FPGA-Verilog] afifo

Description: verilog HDL fifo , verilog HDL fifo , -verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,
Platform: | Size: 2048 | Author: shaohejiang | Hits:
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